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PX1011A/PX1012A Design and Manufacturing FAQ

Q With 0.8mm ball pitch BGA packages, are the PX1011A and PX1012A easy to layout on the PCB?
A In general, it may be true that a 0.8mm ball pitch package makes it more difficult to allow signal escape routing on PCB. However, our PX1011A and PX1012A are specially designed for easy PCB layout. The PX1011A and PX1012A have only 2 signal rings, so that only 1 inner-ring signals need to escape between the balls. In fact, the PX1011A and PX1012A PHYs can be laid out with only 2 PCB signal layers, which have been proven in actual hardware designs.
Q Can the termination resistors at the SSTL-2 interface be removed to reduce component count and lower overall cost?
A The PX1011A and PX1012A do not integrate SSTL-2 termination resistors. External resistors can be removed if the PX1011A or PX1012A is close to the MAC device, but it's a good idea to perform a signal integrity analysis before finalizing the design.
Q Do the PX1011A and PX1012A require external termination resistors to VSS on both the RX_P and RX_N?
A No. External termination resistors are not needed.
Q Do the PX1011A and PX1012A require termination resistors to Vss on both REFCLK_P and REFCLK_N?
A No. External termination resistors are not needed.
Q Should the AC-decoupling capacitors be put close to TX_P and TX_N of the PX1011A/PX1012A or close to the plug-in board edge connector? What is the recommended value of these capacitors?
A The de-coupling capacitors should be put close to TX_P and TX_N of the PX1011A or PX1012A. We recommend using small 0.1μF capacitors.
Q Do the PX1011A and PX1012A have to use the 100MHz reference clock from the PCI Express edge connector for a plug-in card?
A No. The PCI Express specification does not require reference clock sharing, although most plug-in card designs tend to use the 100MHz reference clock from the edge connector to save component count and cost. The PX1011A and PX1012A can use a local reference clock, provided that it is 100MHz ±300ppm and meets the AC specifications of the PCI Express Specifications.
Q Can the VREFS pin of the PX1011A/PX1012A be connected to VTT?
A It is not recommended that VREFS pin be connected to VTT because the SSTL-2 termination voltage VTT is very noisy.
Q Is there any special filtering requirement or recommendation on the various power supplies for PX1011A and PX1012A?
A There is nothing specially required. We recommend the use of ferrite beads and 22μF/10μF/1μF filter capacitors.
Q How should the JTAG pins be terminated for the PX1011A and PX1012A?
A Access to the JTAG interface is provided to the customer for the sole purpose of using a boundary scan for interconnect test verification between other compliant devices that may reside on the board. In normal operation mode (or if JTAG is not used at all), the JTAG TRST_N has to be pulled down. Other JTAG input pins (TDI, TMS, TCLK) can be either pulled up (tied to VDD1) or down (tied to VSS). The TDO pin can be left open.
Q Is it OK to connect the signals from the PCI Express edge connecter to JTAG pins (TMS, TRST_N, TCK, TDI, TDO)?
A It is not a problem that JTAG pins connect to the PCI Express edge connecter.
Q Does the PX1011A/PX1012A support spread-spectrum clocking (SSC)? Does the PHY filter out the SSC when it outputs the 250 MHz RXCLK or is the SSC still present?
A The PX1011A/PX1012A support SSC, and they do not filter out SSC.
Q Is it required to input TXCLK in the reset period?
A No. The TXCLK is not required during the reset.

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