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Frequently asked questions
PCA9500 and PCA9501 FAQ
| Q |
Do the PCA9500 or PCA9501 have 5V-tolerant I/Os? |
| A |
Yes, the PCA9500 and PCA9501 have been designed to tolerate overvoltage conditions on its I/O pins due to hot-swapping of up to 5.5V.
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| Q |
Are the PCA9500 and PCA9501 I2C lines (SCL, SDA) 5V-tolerant? |
| A |
Yes, they are tolerant to overvoltage for the purpose of live insertion capability, and can be connected to a 5V-pull-up bus.
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| Q |
Is the state of the PCA9500 and PCA9501 address pins (A0 .. A5) latched upon power-up like they are in the PCF8574? |
| A |
No. The device address of PCA9500 and PCA9501 can be changed during uptime by changing the state of any address pin.
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| Q |
Can the I2C address of the PCA9500 and PCA9501 E2PROM and the I/O port be changed independently? |
| A |
No. The addresses of both internal devices are each given the same address offset simultaneously with changing settings of the address pins.
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| Q |
How do the PCA9500 and PCA9501 support live insertion? |
| A |
By implementing overvoltage capability on all I/O pins.
Overvoltage conditions should however not be applied to the power supply pin as it is governed by its recommended maximum operating conditions and absolute maximum ratings.
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| Q |
Is it necessary to control the write control (WCn) pin in order to write to the PCA9500 and PCA9501 E2PROM? |
| A |
No. For convenience, WCn may simply be tied permanently to ground, enabling the on-chip high-voltage memory write voltage generator.
An explicit write control signal was implemented on PCA9500 and PCA9501 for the sake of compatibility with legacy types serial E2PROM still widely available on the market.
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| Q |
Do the PCA9500 and PCA9501 require external pull-ups? |
| A |
Not for most pins.
The PCA9500 and PCA9501 include on-board pull-up mechanism on the address (A0 .. A5) and write control (WCn) pins.
The interrupt pin on the PCA9501 (INTn) and the I2C pins, in order to allow bussing, are open-drain type and hence require appropriate external pull-ups.
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| Q |
Is the PCA9501 interrupt function (pin 8) synchronous or asynchronous with respect to the I2C serial clock SCL? |
| A |
Pin INTn for all purposes should be considered asynchronous with respect to SCL.
Designers should avoid relying on SCL to clock in the INTn event to the controller.
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| Q |
What happens if the PTN3500 and PCA9501 are hot-inserted during a transaction? |
| A |
At the time of insertion, any circuit not pre-charging its capacitive load will introduce a minor spike as the capacitance charges, even if the device claims live insertion capability.
The PTN3500 and PCA9501 will present about 3pF.
The customer can best determine the resulting voltage spike, which would correlate to the ratio of the bus' existing capacitance to the new total capacitance, and the bus pull-up resistance.
If the spike is sufficiently small to not exceed I2C noise tolerance levels, the PTN3500 and PCA9501 should work in the customer's design approach.
In general, the PCA9500 and PCA9501 employ a power-on reset that is active for however long the supply takes to reach ~2.4V, after which the device will be actively in reset for an additional 300ns.
Then, it will patiently wait for a start condition.
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| Q |
The three address pins of the PCA9500 and PCA9501 allow multiple devices to share the 2-wire interface. Are multiple devices in parallel still compatible with live insertion? |
| A |
Yes, they are.
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| Q |
How exactly do the I/O ports on the PCA9500 and PCA9501 operate? Are there any port directions bits? |
| A |
There are no port-direction bits.
A logic one must be written to the port from the I2C before data can be read.
If a port bit is accidentally written to a logic low, correct data read from the port cannot be guaranteed.
Further, should a "bus contention" situation occur it is unlikely that 25mA will damage either IC.
Please note that the port contains a register and the I2C can write a logic one to the port register regardless of what voltage is present on the port bit.
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| Q |
The PCA9500 and PCA9501 E2PROM has a self-timed write cycle, 5ms typical, 10ms max. Can the write cycle "done" status be polled over the I2C bus? Or does the I2C master simply have to guarantee that write cycles will not occur any more frequently than tWR, max = 10ms? |
| A |
You can poll the PCA9500 or PCA9501 by simply trying to read or write the E2PROM.
If the E2PROM is not ready, there will be no acknowledge.
Please note that while the E2PROM may be busy, you can read or write the port without waiting.
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| Q |
Are the PCA9500 and PCA9501 compatible with 100kHz operation? |
| A |
Yes, they are.
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| Q |
tPUR implies that a 1ms delay must be enforced after power-up before a read cycle is initiated. What is the behavior of the PCA9500 and PCA9501 if this is not guaranteed? Will the part recover and operate normally after the initial read cycle, which is assumed to be faulty? |
| A |
This timing refers to E2PROM access only.
There is no timing restriction for port access.
The part will recover normally, but data access to the E2PROM during this period cannot be guaranteed.
That is, data may be incorrectly read from or written to the E2PROM.
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More Information
Other Questions
If you have other questions that you would like answered, please contact us.
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